Bio

I am a second year Computer Science PhD student and a Gradudate Research Assitant at Oregon State University. My interest is in HPC systems research to explore memory characterization, power efficiency and performance improvements in high performance workloads. I am advised by Dr. Kyle Hale and I work with folks at HExSA Lab and HiPCastor Lab at OSU. I also collaborate with Dr. Nathan Tallent at Pacific Northwest National Lab.

I received my Masters degree (class of 2021) at Illinois Tech under the supervision of Dr. Hale and started my PhD there, before transfering to OSU. Before my Masters I worked as a software development engineer for 3 years at Temenos (formerly Kony Labs) in Hyderabad, India.

News

Aug 05, 2026	Submitted CURATE paper to WORKS '26.
Jul 13, 2026	Visiting Seattle, WA to attend OSDI '26 conference.
Jul 06, 2026	MEMPOWER paper accepted to CLUSTER '26! 🎉
Jun 28, 2026	Mentoring HExSA Lab REU students over the Summer.

Projects

Hybrid CPU Evaluation: To explore the effects and impact of hybrid core and cache architecture on the performance of highly parallel HPC workloads, this project evaluates various multi-threaded HPC workloads on Intel Alderlake hybrid cores. This project also explores the impact of hybrid cache architecture on parallel shared-data HPC applications. Key take aways from this evaluation: 1) parallel applications with work imbalance (i.e., threads in application perform different amount of work) scale better across hybrid cores when thread affinity is disabled and 2) hybrid cache architecture has very little impact on parallel shared-data applications except for some workloads with locks.

P2P Distributed Task Orchestrator: The goal of this project is to build a framework to enable distributed task execution environment on a P2P (Peer-to-Peer) network. The basic idea is that in a P2P network, each node acts as a task submitter and a task executor. We define a task to be a JRE (Java Runtime Environment) Thread and it contains all the required state for the task. Each node in the network holds a list of tasks that need to be executed and a leader node uses a power-of-two algorithm to distribute tasks among rest of the nodes (including itself). The leader is elected by an election process at the begining of network setup or if the leader experiences a crash stop (initiated by other nodes in the network). [code]

Remote Memory Pool: In order to enable remote memory for userspace applications, existing far/disagregated memory techniques utilize the operating system's pagefault mechanism to alloc/send/recv pages on a remote memory node. However, the pagefault mechanism requires previledge escalation and comes with a performance overhead. The idea of this project is to utilize the Linux kernel's userfaultfd mechanism, which works entirely in the userspace, to send/recv pages to/from a remote node. [code]

Provenance: As part of my summer research project, I implemented a logging/debugging tool, Provenance, to monitor kernel events for Nautilus AeroKernel which is part of the Interweaving Project.

ISA for Dataflow Machines: Many real-world machines (Manchester Dataflow Machine) and execution models (Tagged-token) were proposed to run dataflow programs. The goal of this project is to desgin a novel ISA (Instruction Set Architecture) such that users can develop dataflow programs. The basic idea is that the dataflow program is represented as a graph where nodes represent an instruction (e.g. ADD, SUB, MUL, etc), ingress edges represent input operands and egress edge represents the computed result value.

Publications

MEMPOWER: Efficient Power Management with Fine-grained Memory Analysis and Modeling for HPC Workloads
Nanda Velugoti, Joseph Manzano, Andres Marquez, Nathan Tallent, Kyle C. Hale
[paper] [slides] [code] [CLUSTER '26] (To be appeared)

CURATE: Leveraging LLM Agents to Compose, Catalog, and Deploy Reproducible Workflows
Nolan Cutler, Laura Kuo, Nanda Velugoti, Kathryn Newhart, Renato Figueiredo
[paper] [slides] [code] [SC Workshops '26] (Under review)

Posters

Exploring Fine-grained Memory Analysis for PIM Offloading
Thomas M. Papka, Nanda Velugoti, Kyle C. Hale
[poster] [report] [code] [SC '24]

Memory Disaggregation in Serverless Computing
Joshua Lowe, Nanda Velugoti, Kyle C. Hale
[poster] [report] [code] [SC '24]

Predicting and alleviating bottlenecks in Hybrid CPU and Memory Architectures
Nanda Velugoti, Joseph Manzano, Nathan Tallent, Kyle C. Hale
[poster] [report] [code] [GCASR '23]

Blog

Coming soon...